Benchmark: Layer fidelity and error per layered gate (EPLG)
Benchmarks / System level (whole processor)
The fidelity of a connected layer of two-qubit gates across many qubits, and a size-independent error per layered gate derived from it.
- Level
- System level (whole processor)
- Maintained by
- Proposed by McKay et al. (2023); code in the Qiskit Device Benchmarking repository.
- European
- No
- Reference
- https://arxiv.org/abs/2311.05933
How it is measured
Simultaneous direct randomised benchmarking on disjoint layers of gates; the original paper measured it over 80 to 100 qubits of a 127-qubit Eagle and a 133-qubit Heron processor.
Limitations and criticisms
- Measures gate layers, not complete applications.
- Preprint by one vendor; tools are in a community repository that states it does not define a standard.
Used in European procurements
None of the procurement documents read for this release names it.
Sources
- D. C. McKay et al. (2023). Benchmarking Quantum Processor Performance at Scale. arXiv:2311.05933 (preprint, November 2023). Read: abstract page, retrieved 2026-10-23.
- Qiskit community (2026). Qiskit Device Benchmarking repository. GitHub repository README. Read: repository README, retrieved 2026-10-23.