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Surface code error correction

Algorithms and benchmarks / Error correction (enabling)

The leading quantum error-correcting code for chips with nearest-neighbour connections: many physical qubits on a 2D grid encode one logical qubit, and repeated measurements detect errors that a classical decoder corrects in real time.

Era
Fault-tolerant
Problem class
Error correction (enabling)
Speedup
An enabling technique: it makes long fault-tolerant algorithms possible at a large qubit overhead.

How it works

Data qubits and measurement qubits alternate on a square grid; stabiliser measurements every cycle reveal error syndromes; increasing the code distance suppresses logical errors when physical errors are below a threshold.

Typical use cases

  • The basis of most fault-tolerant resource estimates (Shor, chemistry, Hamiltonian simulation).

Related pages

Resource estimates

No resource estimate with stated assumptions was verified for this family in this release.

Demonstrations

  • 2025: Distance-7 surface code memory on 101 qubits: 0.143% ± 0.003% logical error per cycle, error suppression Λ = 2.14 ± 0.02 per distance step of two, a logical lifetime 2.4 ± 0.3 times the best physical qubit, 1.1 microsecond cycles and a decoder latency of 63 microseconds on average at distance 5. (R. Acharya et al. 2025)

Hardware platforms that fit

  • Superconducting qubits: A distance-7 surface code memory with 101 qubits ran below threshold with a 1.1 microsecond cycle (Acharya et al. 2025) on a processor of Google Quantum AI, whose processors are superconducting (Arute et al. 2019).
  • Neutral atoms: Reconfigurable atom arrays scaled a surface code from distance 3 to 7 to improve a logical two-qubit gate (Bluvstein et al. 2023).

What you need to run it

Classical simulation
Stabiliser simulators (such as Stim) simulate surface-code circuits with thousands of qubits efficiently, because the circuits are Clifford.
Noisy hardware (NISQ)
Not applicable for this family.
Fault-tolerant machine
Physical error rates below the threshold, fast mid-circuit measurement and reset, and a real-time decoder; cycle times around 1 microsecond on superconducting chips.
Annealer or analogue simulator
Not applicable for this family.

Calculate the memory of a simulation

Where to run it in Europe

Superconducting qubits

Neutral atoms

The full infrastructure catalogue · The infrastructure deployment tracker

Software

European tools in the software directory

Other open-source frameworks

  • Stim (Google Quantum AI (United States); non-European)

A listing is not an endorsement; check each tool for the features you need.

Limitations and open questions

  • Many physical qubits per logical qubit: Bravyi et al. (2024) put the surface code at about 3,000 physical qubits for 12 logical qubits, and the fault-tolerant estimates reach millions of physical qubits.
  • Non-Clifford gates need magic states, which cost extra space and time.
  • Decoding must keep up with the cycle time in real time.

In the Quantum Algorithm Zoo

No matching Zoo entry was found on 23 October 2026; the Zoo lists algorithms with a proven or conjectured speedup, not this family.

Index: the Quantum Algorithm Zoo by Stephen P. Jordan, last updated 2026-09-10, checked 2026-10-23. The portal links to it and copies no description from it. Browse the full Quantum Algorithm Zoo (external site)

Named in European procurements

None of the procurement documents read for this release names it.

Sources

  1. A. G. Fowler, M. Mariantoni, J. M. Martinis, A. N. Cleland (2012). Surface codes: Towards practical large-scale quantum computation. Phys. Rev. A 86, 032324 (2012); arXiv:1208.0928. Read: abstract page, retrieved 2026-10-23.
  2. R. Acharya et al. (2025). Quantum error correction below the surface code threshold. Nature 638, 920 (2025); arXiv:2408.13687. Read: abstract page, retrieved 2026-10-23.
  3. F. Arute et al. (2019). Quantum supremacy using a programmable superconducting processor. Nature 574, 505 (2019); supplementary information on arXiv:1910.11333. Read: arXiv page of the supplementary information, retrieved 2026-10-23.
  4. S. Bravyi, A. W. Cross, J. M. Gambetta, D. Maslov, P. Rall, T. J. Yoder (2024). High-threshold and low-overhead fault-tolerant quantum memory. Nature 627, 778 (2024); arXiv:2308.07915. Read: abstract page, retrieved 2026-10-23.
  5. D. Bluvstein et al. (2023). Logical quantum processor based on reconfigurable atom arrays. Nature (published online 2023), DOI 10.1038/s41586-023-06927-3; arXiv:2312.03982. Read: abstract page, retrieved 2026-10-23.